Memory bandwidth optimizations for wide-bus machines
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. i, 466-475
- https://doi.org/10.1109/hicss.1993.270618
Abstract
The authors describe and evaluate the effectiveness of some code improvement techniques that are designed to take advantage of wide-bus machines (WBMs): that is, a microprocessor with a memory bus width at least twice the size of the integer data type handled by the processor and assumed by the programmer. They discuss some compiler optimizations that take advantage of the increased bandwidth available from a wide bus. The investigations show that WBMs can expect reduction in memory bus cycles on the order of 5 to 15%. Using new code improvement algorithms designed to exploit the availability of a wide bus, the studies show that, for many memory-insensitive algorithms, it is possible to reduce the number of memory loads and stores by 30 to 40%.Keywords
This publication has 10 references indexed in Scilit:
- Code generation for streaming: an access/execute mechanismPublished by Association for Computing Machinery (ACM) ,1991
- The cache performance and optimizations of blocked algorithmsPublished by Association for Computing Machinery (ACM) ,1991
- The priority-based coloring approach to register allocationACM Transactions on Programming Languages and Systems, 1990
- The cache DRAM architecture: a DRAM with an on-chip cache memoryIEEE Micro, 1990
- Ease: an environment for architecture study and experimentationPublished by Association for Computing Machinery (ACM) ,1990
- Improving register allocation for subscripted variablesPublished by Association for Computing Machinery (ACM) ,1990
- A portable global optimizer and linkerPublished by Association for Computing Machinery (ACM) ,1988
- Code selection through object code optimizationACM Transactions on Programming Languages and Systems, 1984
- Register allocation and exhaustive peephole optimizationSoftware: Practice and Experience, 1984
- Using cache memory to reduce processor-memory trafficPublished by Association for Computing Machinery (ACM) ,1983