A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit
- 1 December 2002
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 37 (12) , 1822-1830
- https://doi.org/10.1109/jssc.2002.804342
Abstract
No abstract availableKeywords
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