Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 605-608
- https://doi.org/10.1109/iedm.1998.746431
Abstract
To sustain the silicon CMOS scaling beyond 100 nm, an alternate gate dielectric with K>7 is needed. The deposited high K dielectrics (metal oxides) have nonstoichiometric composition and therefore have large electrical defects (traps) in the bulk of the dielectric and at the dielectric/semiconductor interface. In this paper, we report a novel doping method to quench traps in thin films of Al/sub 2/O/sub 3/ (K>8). By adding small amounts of dopants such as Zirconium (Zr) or Silicon (Si), we have achieved /spl sim/10nm thick aluminum oxide films with record low leakage current (10.Keywords
This publication has 3 references indexed in Scilit:
- Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A Novel High K Inter-poly Dielectric(IPD), A1/sub 2/O/sub 3/ For Low Voltage/high Speed Flash memories: erasing in msecs at 3.3VPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- ONO Interpoly Dielectric Scaling Limit For Non-volatile Memory DevicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993