Improving the performance and efficiency of an adaptive amplification operation using configurable hardware
- 11 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 267-275
- https://doi.org/10.1109/fpga.2000.903414
Abstract
An adaptive amplification operation has been designed and tested in configurable hardware for a computationally intensive object recognition system. This configurable system provides over forty-one times the throughput of an industry-standard embedded processor by exploiting the bandwidth of internal block memories and parallelism within the algorithm. Operating at less than one half the power of the programmable processor, the configurable approach performs the computation with 90 times less energy. The improvements in both performance and power are obtained by customizing the datapath, memory interfaces, and control to the amplification algorithm.Keywords
This publication has 5 references indexed in Scilit:
- Field programmable gate array based radar front-end digital signal processingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A CAD suite for high-performance FPGA designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Flexible image acquisition using reconfigurable hardwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- FPGA-based sonar processingPublished by Association for Computing Machinery (ACM) ,1998
- Configurable computing solutions for automatic target recognitionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1996