Measuring 6D Chip Alignment in Multi-Chip Packages

1 January 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 19300395,p. 1307-1310
https://doi.org/10.1109/icsens.2007.4388650

Abstract

We present techniques to detect all six degrees of positioning of one CMOS chip relative to another using capacitance measurements. Unlike other capacitive sensing schemes, these solutions achieve sub-femofarad resolution by directly measuring coupling capacitance and rejecting parasitic capacitances. We apply these techniques to dynamically monitor the 6D alignment of chips in multi-chip packages.

Keywords

This publication has 5 references indexed in Scilit:

Electronic alignment for proximity communication
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004
Proximity communication
IEEE Journal of Solid-State Circuits, 2004
Atto-Farad Measurement and Modeling of On-Chip Coupling Capacitance
IEEE Electron Device Letters, 2004
An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
An on-chip coupling capacitance measurement technique
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002