Design of universal test sequences for VLSI
- 1 January 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Information Theory
- Vol. 31 (1) , 10-17
- https://doi.org/10.1109/tit.1985.1057003
Abstract
A test sequence is called(s,t)-universal if it exercises every function depending on t or fewer inputs on a very large scale integration (VLSI) chip withsinputs. Randomized and deterministic procedures are deseribed for the design of(s,t)-universal sequences and for the signature analysis of the test outputs.Keywords
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