Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing

1 February 1983

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-32 (2) , 190-194
https://doi.org/10.1109/TC.1983.1676202

Abstract

One has a shift register of length n and a collection of designated subsets of {0, 1,···, n-1}. The problem is to devise a method for feeding a string of bits into the shift register in such an order that, for each designated subset S = {k1,···, kr}, if one keeps track of the bit patterns appearing at the corresponding positions k1, ···, krof the shift register, all 2r possible bit patterns will ultimately appear at those positions. A simple and efficient solution to this problem, derived from the connections between polynomials over finite fields and linear feedback shift registers, is presented. Applications of this solution to the problem of VLSI self-testing are discussed and illustrated.

Keywords

This publication has 2 references indexed in Scilit:

Design of universal test sequences for VLSI
IEEE Transactions on Information Theory, 1985
Built-in test for complex digital integrated circuits
IEEE Journal of Solid-State Circuits, 1980