Failure mechanisms in large-scale integrated circuits

Abstract
A study was made of the factors affecting the reliability of large-scale integrated (LSI) circuits. Particular attention was given to the effect on array reliability of the additional processing steps required to obtain multilevel metalization. The additional significant steps are low temperature deposition of a second dielectric layer on metalized LSI wafers, etching of vias through the second dielectric, and second level metalization. Consideration was also given to the effect of other trends in LSI, such as the use of smaller geometry and closer spacings. Possible new failure modes in multilevel arrays are: 1) shorts or increased leakage through or along deposited second layer dielectrics, 2) opens or increased series resistance in conductors, and 3) silicon surface effects. A review of literature on LSI was supplemented by results of a number of concurrent LSI programs and experimental studies. Test vehicles were designed to provide fundamental information about each of the categories of failure. Data obtained using these test vehicles to evaluate the multilevel metalized array structures are presented. A discussion concerning the merits and limitations of the specially designed test vehicles for process development, process control, and reliability tests is given. It is concluded that with the proper in-process controls, tests and screens, LSI arrays will be substantially more reliable per function accomplished than are conventional integrated circuits.

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