Improved voltage margins using linear error-correcting codes in resistor-logic demultiplexers for nanoelectronics

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Abstract
We present a family of demultiplexer circuit designs based on linear error-correcting codes, which can be laid out on nanoelectronic crossbar structures. The crossbars are assume dt o have configurable resistors at the crosspoint junctions, and the demultiplexer circuits are therefore implemented using resistor logic. In general, resistor logic offers poor voltage margins when implementing digital circuits, but the circuit construction we present allows us to circumvent this problem by capitalizing on the minimum-distance property of codes to avoid certain problem cases, and thus achieve a much larger voltage margin. For each linear code, there is ac orresponding demultiplexer circuit prescribed by this construction, and thus a large family of demultiplexer circuits is defined. When a demultiplexer of a given size is needed in a system, this circuit family offers to the designer a set of alternative demultiplexer circuit designs, in which increasing voltage margins can be achieved, but at the cost of increasing circuit area. We analyse a demultiplexer circuit based on an arbitrary linear code. For this general case, we give the encoding computation prescribed by the code, give the configuration pattern prescribed by the code for the crossbar part of the circuit, calculate the output voltage on each of the demux output lines as a function of the current input signal, calculate the worst-case voltage margin, and calculate cost parameters measuring the increased area consumed by the circuit. This code-based demultiplexer circuit design makes it possible to handle the voltage-margin problem of resistor logic, and thus makes it feasible to build relatively large demultiplexers using nano-scale crossbars with configurable resistors at the crossbar junctions.