A 480 MHz RISC microprocessor in a 0.12 μm L/sub eff/ CMOS technology with copper interconnects
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors. These technology features have helped to increase the microprocessor internal clock frequency to 480 MHz at 2.0 V and 85/spl deg/C, and at the fast end of the process distribution. When operating at room temperature, the clock frequency increases to over 500 MHz. The microprocessor architecture includes two 32 KB L1 caches, one for data and one for instructions, integrated L2 cache controller working with L2 caches of 256 KB, 512 KB, or 1MB, and I/Os interfacing with the external bus using industry-standard 3.3 V. The microprocessor is implemented in 2.5 V CMOS technology and has migrated to 1.8 V CMOS technology.Keywords
This publication has 2 references indexed in Scilit:
- Full copper wiring in a sub-0.25 μm CMOS ULSI technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controllerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002