Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs

This publication has 8 references indexed in Scilit:

• Virtex FPGA implementation of a polyphase filter for sample rate conversion
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions
  Journal of Signal Processing Systems, 1999
• Comments on "Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters"
  IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1998
• A fast constant coefficient multiplier for the XC6200
  Published by Springer Nature ,1996
• Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters
  IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995
• Use of minimum-adder multiplier blocks in FIR digital filters
  IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995
• Greedy hardware optimization for linear digital circuits using number splitting and refactorization
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
• Efficient synthesis of distributed vector multipliers
  Microprocessing and Microprogramming, 1993