iEDISON: an interactive statistical design tool for MOS VLSI circuits
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Statistical MOS VLSI circuit optimization with non-nested experimental designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Signal-to-Noise Ratios, Performance Criteria, and TransformationsTechnometrics, 1988
- Application of statistical design and response surface methods to computer-aided VLSI device designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Elimination of process-dependent clock skew in CMOS VLSIIEEE Journal of Solid-State Circuits, 1986
- A Methodology for Worst-Case Analysis of Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- An Integrated and Efficient Approach for MOS VLSI Statistical Circuit DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986