Synthesizing embedded speed-optimized architectures
- 1 March 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 28 (3) , 242-252
- https://doi.org/10.1109/4.209990
Abstract
No abstract availableKeywords
This publication has 15 references indexed in Scilit:
- Synthesizing Embedded Speed-optimized ArchitecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- An algorithm for component selection in performance optimized schedulingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Combined hardware selection and pipelining in high-performance data-path designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Optimal VLSI Architectural SynthesisPublished by Springer Nature ,1992
- Optimal synthesis of multichip architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- A formal approach to the scheduling problem in high level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Synthesis of application-specific multiprocessor architecturesPublished by Association for Computing Machinery (ACM) ,1991
- Integer and Combinatorial OptimizationPublished by Wiley ,1988
- Solving Large-Scale Zero-One Linear Programming ProblemsOperations Research, 1983
- A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983