A novel reduced swing CMOS bus interface circuit for high speed low power VLSI systems

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Abstract
Major applications of CMOS VLSIs require the use of high fan out busses, such as Asynchronous Transfer Mode (ATM) cross-bar switching matrices, high performance processors employing multiple busses, and high performance CPLDs using universal interconnection matrices. The bus interface circuits are major contributors to the power dissipation of a system for achieving high clocking frequencies. To address the increased power dissipation for high speed busses, a novel reduced voltage swing CMOS bus interface circuit is presented here. The design is a combination of drivers and receivers which perform level translation without any need to reduce the supply voltage. The simulation results based on these circuits show significant enhancements on both speed and power in comparison with the conventional CMOS tri-state driver techniques. To further assess this design, an LSI 32/spl times/32 crosspoint switch is implemented to be used for ATM communication systems. The chip uses a 1.2 /spl mu/m CMOS process with a die size of 4/spl times/3 mn, and has pseudo ECL input/output compatible interfaces which can operate at 250 Mb/s serial communication links per channel. The power consumption at 250 Mb/s is 0.6 W which is 60% lower than other published results for a similar switch. Without the input/output pad restrictions, the simulation results indicate that the switching matrix is capable of running at 622 Mb/s with a similar power reduction.

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