Automatic layout and optimization of static CMOS cells
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 180-185
- https://doi.org/10.1109/iccd.1988.25686
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Layout optimization of static CMOS functional cellsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Optimal Chaining of CMOS Transistors in a Functional CellIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A Ranking Algorithm for MOS Circuit LayoutsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Linear algorithms for two CMOS layout problemsPublished by Springer Nature ,1986
- Optimal Layout of CMOS Functional ArraysIEEE Transactions on Computers, 1981
- Wire routing by optimizing channel assignment within large aperturesPublished by Association for Computing Machinery (ACM) ,1971