Development of advanced 3D chip stacking technology with ultra-fine interconnection

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 05695503,p. 541-546
https://doi.org/10.1109/ectc.2001.927780

Abstract

The development of 3D chip stacking technology with ultra-fine pitch interconnection initiated in 1999, which is a part of "Ultra High-Density Electronic System Integration" project. The development involves the backend of wafer fabrication process, packaging and testing. The extended study revealed possibilities and advantages of 3D chip stacking structure with ultra-fine interconnection.

Keywords

STACKING
INTEGRATED CIRCUIT INTERCONNECTIONS
INTEGRATED CIRCUIT TECHNOLOGY
LARGE SCALE INTEGRATION
FABRICATION
CHIP SCALE PACKAGING
ELECTRONICS PACKAGING
ETCHING
TESTING
WAFER SCALE INTEGRATION

This publication has 2 references indexed in Scilit:

Copper bump bonding with electroless metal cap on 3 dimensional stacked structure
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
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IEEE Micro, 1998