The TigerSHARC DSP architecture

1 January 2000

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro

Vol. 20 (1) , 66-76
https://doi.org/10.1109/40.820055

Abstract

This highly parallel DSP architecture based on a short-vector memory system incorporates techniques found in general-purpose computing. It promises sustained performance close to its peak computational rates of 900 MFLOPS (32-bit floating-point) or 3.6 BOPS (16-bit fixed-point).

Keywords

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