Efficient power co-estimation techniques for system-on-chip design
- 7 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 16 references indexed in Scilit:
- Profile-driven Program Synthesis For Evaluation Of System Power DissipationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Cycle-accurate simulation of energy consumption in embedded systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A low power hardware/software partitioning approach for core-based embedded systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Sequential circuit design using synthesis and optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A case study on modeling shared memory access effects during performance analysis of HW/SW systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Software timing analysis using HW/SW cosimulation and instruction set simulatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast instruction cache simulation strategies in a hardware/software co-design environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1999
- High-Level Power Analysis and OptimizationPublished by Springer Nature ,1998
- Hardware-Software Co-Design of Embedded SystemsPublished by Springer Nature ,1997
- Low Power Design MethodologiesPublished by Springer Nature ,1996