Chortle: a technology mapping program for lookup table-based field programmable gate arrays
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 24 (0738100X) , 613-619
- https://doi.org/10.1109/dac.1990.114927
Abstract
An algorithm is described for technology mapping of combinational logic into field programmable gate arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle, uses the fact that a K-input lookup table can implement any Boolean function of K inputs and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparison with the MIS II technology mapper, on MCNC-89 LOGIC Synthesis benchmarks Chortle achieves superior results in significantly less time.<>Keywords
This publication has 7 references indexed in Scilit:
- Automatic synthesis and technology mapping of combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 9000-gate user-programmable gate arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- McMAP: a fast technology mapping procedure for multi-level logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Technology mapping for standard-cell generatorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The effect of logic block complexity on area of programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A 5000-gate CMOS EPLD with multiple logic and interconnect arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- DAGON: technology binding and local optimization by DAG matchingPublished by Association for Computing Machinery (ACM) ,1987