Circuit performance of CMOS technologies with silicon dioxide and reoxidized nitrided oxide gate dielectrics

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Abstract
The circuit performance of CMOS technologies with silicon dioxide (SiO/sub 2/) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V/sub GS/<or=5 V and B/sub DS/<or=5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO/sub 2/ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower mu /sub p/ (hole mobility) of RONO p-channel devices. At 300 K, mu /sub p/(RONO) is 14-8% smaller than mu /sub p/(SiO/sub 2/) over the entire range of gate biases, while mu /sub n/(RONO) (electron mobility of n-channel RONO devices) is also smaller than mu /sub n/(SiO/sub 2/) and reaches only 96% of mu /sub n/(SiO/sub 2/) at V/sub GS/=5 V. At 100 K, mu /sub n/(RONO)/ mu /sub n/(SiO/sub 2/) at V/sub GS/=5 V is increased to 1.10, however, mu /sub p/(RONO)/ mu /sub p/(SiO/sub 2/) at V/sub GS/=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO/sub 2/ inverters.