CMOS/SOS memory circuits for radiation environments
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 669-676
- https://doi.org/10.1109/jssc.1978.1051117
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Radiation-Hardened Silicon-Gate CMOS/SOSIEEE Transactions on Nuclear Science, 1977
- Two static 4K clocked and nonclocked RAM designsIEEE Journal of Solid-State Circuits, 1977
- Process technology for radiation-hardened CMOS integrated circuitsIEEE Journal of Solid-State Circuits, 1976
- A threshold voltage controlling circuit for short channel MOS integrated circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1976
- Substrate and load gate voltage compensationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1976
- Prompt Radiation Damage and Short Term Annealing in CMOS/SOS DevicesIEEE Transactions on Nuclear Science, 1976
- Investigation of Radiation Effects and Hardening Procedures for CMOS/SOSIEEE Transactions on Nuclear Science, 1975
- Peripheral circuits for one-transistor cell MOS RAM'sIEEE Journal of Solid-State Circuits, 1975