Don't care set specifications in combinational and synchronous logic circuits
- 1 March 1993
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 12 (3) , 365-388
- https://doi.org/10.1109/43.215001
Abstract
We present a unified framework for the specification and computation of don't care conditions for combinational and synchronous multiple-level digital circuits. We characterize such circuits in terms of graphs, logic functions and don't care conditions induced by the external and internal interconnections. We model the replacement of a gate in a synchronous logic network by a perturbation of the corresponding logic function, and show that the don't care conditions for the gate optimization represent the bound on this perturbation. We present algorithms to compute such don't care conditions in both the combinational and synchronous case. We comment on the implementation of the algorithms and on the experimental results.This publication has 22 references indexed in Scilit:
- Redundancies and don't cares in sequential logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Consistency and observability invariance in multi-level logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Observability don't care sets and Boolean relationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Retiming and resynthesis: optimizing sequential networks with combinational techniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Efficient implementation of a BDD packagePublished by Association for Computing Machinery (ACM) ,1990
- Boolean ReasoningPublished by Springer Nature ,1990
- A synthesis and optimization procedure for fully and easily testable sequential machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- ASYL: A Rule-Based System for Controller SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- The identification of a minimal feedback vertex set of a directed graphIEEE Transactions on Circuits and Systems, 1975