Redundancies and don't cares in sequential logic synthesis
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 491-500
- https://doi.org/10.1109/test.1989.82332
Abstract
The authors explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty state transition graph (STG) that is equivalent to the STG of the true machine. The authors present a classification of redundant faults in sequential circuits composed of single or interacting finite-state machines. Don't care sets can be defined for each class of redundancy, and optimally exploiting these don't care conditions results in the implicit elimination of any such redundancies in a given circuit. In cascaded and interconnected sequential circuits, sequential don't cares are required to eliminate redundancies. The authors present preliminary experimental results which indicate that by exploiting these don't cares medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times.Keywords
This publication has 10 references indexed in Scilit:
- Easily testable PLA-based finite state machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis and optimization procedures for fully and easily testable sequential machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- MUSTANG: state assignment of finite state machines targeting multilevel logic implementationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Multi-level logic minimization using implicit don't caresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Test generation for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Redundancy and Don't Cares in Logic SynthesisIEEE Transactions on Computers, 1983
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966
- Minimizing the Number of States in Incompletely Specified Sequential Switching FunctionsIEEE Transactions on Electronic Computers, 1959