A multilevel tungsten interconnect technology
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 466-469
- https://doi.org/10.1109/iedm.1988.32856
Abstract
A multilevel tungsten (W) interconnect technology which is inherently planar has been developed to meet metallisation requirements for VLSI. The W interconnect technology relies on implanting Si into oxide channels, which are later selectively filled with W. The technology has been extended to realize three levels of W metallization. Its advantages include a planar surface after each level of metallization, self-aligned and stacked vias, and high resistance to electromigration. The minimum metal pitch is 2 mu m at all levels. Line resistivity is approximately 7 mu Omega -cm, and contact resistance is less than 0.5 Omega /contact.Keywords
This publication has 1 reference indexed in Scilit:
- High-density high-reliability tungsten interconnection by filled interconnect groove metallizationIEEE Transactions on Electron Devices, 1988