The Effect of Profile Design, Bias Conditions and Load Impedance on Inter-Modulation Distortion in C-Band GaAs Power FETs
- 1 October 1984
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 821-826
- https://doi.org/10.1109/euma.1984.333451
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- Graded channel FET's: Improved linearity and noise figureIEEE Transactions on Electron Devices, 1978
- Profile design for distortion reduction in microwave field-effect transistorsElectronics Letters, 1978