WSI architecture for L-U decomposition: a radar array processor

Publisher Website

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/icwsi.1990.63889

Abstract

No abstract available

Keywords

This publication has 3 references indexed in Scilit:

A wafer-scale 170000-gate FFT processor with built-in test circuits
IEEE Journal of Solid-State Circuits, 1988
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers, 1986
The Design of Optimal Systolic Arrays
IEEE Transactions on Computers, 1985