A wafer-scale 170000-gate FFT processor with built-in test circuits
- 1 April 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 23 (2) , 336-342
- https://doi.org/10.1109/4.993
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- Multi-chip packaging technology for VLSI-based systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- Silicon hybrid wafer-scale package technologyIEEE Journal of Solid-State Circuits, 1986
- The dynamically reconfigurable CAP Array Chip IIEEE Journal of Solid-State Circuits, 1986
- A giant chip multigate transistor ROM circuit designIEEE Journal of Solid-State Circuits, 1986
- A wafer-scale digital integrator using restructurable VSLIIEEE Transactions on Electron Devices, 1985
- A wafer with electrically programmable interconnectionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A defect-tolerant design for full-wafer memory LSIIEEE Journal of Solid-State Circuits, 1984
- A 4-Mbit Full-Wafer ROMIEEE Journal of Solid-State Circuits, 1980
- A 1Mb full wafer MOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Fault tolerant 92160 bit multiphase CCD memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977