Silicon hybrid wafer-scale package technology
- 1 October 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (5) , 845-851
- https://doi.org/10.1109/jssc.1986.1052616
Abstract
No abstract availableKeywords
This publication has 18 references indexed in Scilit:
- Ellipsometric Study of Orientation‐Dependent Etching of Silicon in Aqueous KOHJournal of the Electrochemical Society, 1985
- Silicon-On-Silicon PackagingIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1984
- Area and Delay Penalties in Restructurable Wafer-Scale ArraysPublished by Springer Nature ,1983
- Advanced planar metallization with polymer for VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- On Possible Thermal Degradation in Spirally Programmed Interconnection Wafer TechnologyIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1981
- A 4-Mbit full-wafer ROMIEEE Transactions on Electron Devices, 1980
- Planar multilevel interconnection technology employing a polyimideIEEE Journal of Solid-State Circuits, 1978
- Wafer-scale integration-a fault-tolerant procedureIEEE Journal of Solid-State Circuits, 1978
- Active memory design using discretionary wiring for LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1967
- A discretionary wiring system as the interface between design automation and semiconductor array manufactureProceedings of the IEEE, 1967