Enabling high-speed turbo-decoding through concurrent interleaving
- 25 June 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 897
- https://doi.org/10.1109/iscas.2002.1009986
Abstract
Turbo-Codes are among the most advanced channel coding schemes and are already part of the 3rd Generation Wire- less Communication standards. Future applications, how- ever, will have a demand for higher throughput than the cur- rently targeted 2Mbit/s, leading to a need for highly paral- lelized architectures for Turbo-Decoding. Those where un- til now nearly infeasible because the component decoders are separated by interleavers, which form a bottleneck be- tween them. This paper presents for the first time architectures that perform concurrent instead of sequential interleaving, thus widening the interleaver bottleneck and enabling paral- lelized high-speed Turbo-Decoders. As no limitations on the interleaver design are implied, standard compliant Turbo-Decoders for high throughput are now feasible. Optimizations for high degrees of parallelization are de- rived, applied, and validated using our simulated and syn- thesized register transfer level model. Thus, a whole design space is provided instead of just a single architecture.Keywords
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