Radiation Test and Simulation of CMOS/SOS/ Si-Gate ALU and ROM Devices

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Abstract
This paper presents the results of transient radiation tests on a Carry-Look-Ahead Arithmetic Logic Unit (ALU), the computer simulation of the transient response of this ALU device, and a proposed transient radiation-hardened design for a Read Only Memory (ROM). Experimental results demonstrate the validity of simple SOS device predictions of failure levels for the more complex ALU devices. ALU samples were fabricated with four types of insulators; namely: Al2O3, ion-implanted SiO2, dry SiO2, and wet SiO2. These devices were specially made to investigate total dose hardness and to check the transient hardness of the fabrication on a sapphire substrate. Circuit design and sizing rules to achieve transient hardness were not utilized. Devices were exposed to 10-MeV electron pulses of 20 and 100 ns in a static and an active mode, with inputs activated by six basic test patterns. Upset failure did not occur in the 20-ns pulse tests for all exposure conditions and dose rates up to and including the maximum rate of 1.3 × 1010 rads (Si)/s. The 100-ns pulse tests indicate that the failure level is 3.5 × 1010 rads (Si)/s, whereas the pass level is 2 × 1010 rads (Si)/s. The worst-case exposure conditions are the static mode of operation with the chip outputs in a high state. In order to explain the test results, a simple circuit model of a limited part of the chip output circuit was derived for the static mode of operation and output high.

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