Pipelining: just another transformation
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 13 references indexed in Scilit:
- Automatic synthesis of time-stationary controllers for pipelined data pathsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Algorithm transformations for unlimited parallelismPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Retiming synchronous circuitryAlgorithmica, 1991
- Fast prototyping of datapath-intensive architecturesIEEE Design & Test of Computers, 1991
- Finite state machine has unlimited concurrencyIEEE Transactions on Circuits and Systems, 1991
- A formal approach to the scheduling problem in high level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Available instruction-level parallelism for superscalar and superpipelined machinesPublished by Association for Computing Machinery (ACM) ,1989
- Loop optimization in register-transfer scheduling for DSP-systemsPublished by Association for Computing Machinery (ACM) ,1989
- Software pipelining: an effective scheduling technique for VLIW machinesPublished by Association for Computing Machinery (ACM) ,1988
- Sehwa: a software package for synthesis of pipelines from behavioral specificationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988