Nanoscale Coulomb blockade memory and logic devices
- 25 May 2001
- journal article
- Published by IOP Publishing in Nanotechnology
- Vol. 12 (2) , 155-159
- https://doi.org/10.1088/0957-4484/12/2/317
Abstract
This paper gives a brief review of our recent work done in the area of nanometre-scale Coulomb blockade (CB) memory and logic devices, that enable us to realize future electron-number scalability by overcoming inherent problems to conventional semiconductor devices. We introduce multiple-tunnel junctions (MTJs), naturally formed in heavily doped semiconductor nanowires, as a key building block for our CB devices. For memory applications, the hybrid MTJ/MOS cell architecture is described, and its high-speed RAM operation is investigated. For logic applications the binary decision diagram logic is discussed as a suitable architecture for low-gain MTJ transistors.Keywords
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