An Effective Test Generation System for Sequential Circuits
- 1 January 1986
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 250-256
- https://doi.org/10.1109/dac.1986.1586097
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- PODEM-X: An Automatic Test Generation System for VLSI Logic StructuresPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- 9-V Algorithm for Test Pattern Generation of Combinational Digital CircuitsIEEE Transactions on Computers, 1978
- EBT: A Comprehensive Test Generation Technique for Highly Sequential CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978
- Polynomially Complete Fault Detection ProblemsIEEE Transactions on Computers, 1975
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966