Impact of distributed gate resistance on the performance of MOS devices
- 1 November 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 41 (11) , 750-754
- https://doi.org/10.1109/81.331530
Abstract
This paper describes the impact of gate resistance on cut-off frequency (f/sub T/), maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths. The value of f/sub T/ is proven to be independent of gate resistance even for distributed structures. An exact relation for f/sub max/ is derived and it is shown that, to predict f/sub max/, thermal noise, and time response, the distributed gate resistance can be divided by a factor of 3 and lumped into a single resistor in series with the gate terminal.<>Keywords
This publication has 3 references indexed in Scilit:
- Room temperature 0.1 μm CMOS technology with 11.8 ps gate delayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 89-GHz f/sub T/ room-temperature silicon MOSFETsIEEE Electron Device Letters, 1992
- Microwave Properties of Schottky-barrier Field-effect TransistorsIBM Journal of Research and Development, 1970