Room temperature 0.1 μm CMOS technology with 11.8 ps gate delay
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 131-134
- https://doi.org/10.1109/iedm.1993.347382
Abstract
We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics.Keywords
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