A 1.8 V 36 mW DSP for the half-rate speech codec

23 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 371-374
https://doi.org/10.1109/cicc.1996.510578

Abstract

A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.

Keywords

DIGITAL SIGNAL PROCESSING
SPEECH CODECS
REGISTERS
FINITE IMPULSE RESPONSE FILTER
THROUGHPUT
ENERGY CONSUMPTION
RANDOM ACCESS MEMORY
READ ONLY MEMORY
CIRCUIT SYNTHESIS
PREDICTION ALGORITHMS

This publication has 2 references indexed in Scilit:

A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Low-power CMOS digital design
IEEE Journal of Solid-State Circuits, 1992