Reducing transition counts in arithmetic circuits
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We present an approach to reducing the average number of signal transitions (T/sub /spl alpha//spl nu//) in the design of sign-detection and comparison of magnitudes. Our approach reduces Ta/sub /spl nu// from 21n/8 (n-operand precision in bits) to 8.5 in the case of iterative implementation, and from 5n to 5+n/8 in the tree network case. The approach is applicable to other arithmetic problems.Keywords
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