A CMOS 12K gate array with flexible 10Kb memory

Abstract

A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.

Keywords

RANDOM ACCESS MEMORY
VERY LARGE SCALE INTEGRATION
LOGIC CIRCUITS
READ-WRITE MEMORY
LOGIC GATES
STRONTIUM
LOGIC DESIGN
WIRING
CMOS LOGIC CIRCUITS
DELAY ESTIMATION

This publication has 1 reference indexed in Scilit:

A 20ns CMOS functionable gate array with a configurable memory
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983