Design of Testable Structures Defined by Simple Loops
- 1 November 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-30 (11) , 875-884
- https://doi.org/10.1109/TC.1981.1675718
Abstract
A methodology is given for generating combinational structures from high-level descriptions (using assignment statements, "if" statements, and single-nested loops) of register-transfer (RT) level operators. The generated structures are cellular, and are interconnected in a tree structure. A general algorithm is given to test cellular tree structures with a test length which grows only linearly with the size of the tree. It is proved that this test length is optimal to within a constant factor. Ways of making the structures self-checking are also indicated.Keywords
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