Testing for faults in combinational cellular logic arrays
- 1 January 1967
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 144, 161-174
- https://doi.org/10.1109/focs.1967.33
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- Fault Testing and Diagnosis in Combinational Digital CircuitsIEEE Transactions on Computers, 1968
- Redundancy for LSI Yield EnhancementIEEE Journal of Solid-State Circuits, 1967
- On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic NetsIEEE Transactions on Electronic Computers, 1966
- Bulk Processing in Distributed Logic MemoryIEEE Transactions on Electronic Computers, 1965
- Cobweb cellular arraysPublished by Association for Computing Machinery (ACM) ,1965
- Cutpoint Cellular LogicIEEE Transactions on Electronic Computers, 1964
- A comparison of sequential and iterative circuitsTransactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics, 1960