Partitioned-charge-based modeling of bipolar transistors for non-quasi-static circuit simulation

1 December 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 7 (12) , 652-654
https://doi.org/10.1109/EDL.1986.26508

Abstract

The concept of partitioned-charge-based (PC) modeling of bipolar transistors is developed and demonstrated, and shown to be fundamentally superior to conventional quasi-static charge-control modeling, the basis of the common (capacitance-based) Gummel-Poon (GP) equivalent circuit. SPICE transient simulations with PC and GP models are contrasted to show a first-order accounting for non-quasi-static (NQS) delay in the PC model which is not accounted for in the GP model. Additional model contrasts in the small-signal domain, compared with exact ac solutions, confirm the superiority of the PC model, the characterization of which is in fact no more tedious than that of the GP model.

Keywords

This publication has 4 references indexed in Scilit:

SPICE Simulation of SOI MOSFET Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
Significance of the channel—Charge partition in the transient MOSFET model
IEEE Transactions on Electron Devices, 1986
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