On Fault Detection in CMOS Logic Networks

1 January 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 0738100X,p. 50-56
https://doi.org/10.1109/dac.1983.1585625

Abstract

This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.

Keywords

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