A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (4) , 859-868
- https://doi.org/10.1109/4.34062
Abstract
No abstract availableKeywords
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