A reconfigurable decision-feedback equalizer chip set architecture for high bit-rate QAM digital modems
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1185-1188 vol.2
- https://doi.org/10.1109/icassp.1991.150591
Abstract
A 70-MHz decision-feedback equalizer chip set using novel architecture and circuit design techniques that can accommodate a wide variety of modulation formats (QPSK, 16-, 64-, 256-QAM) is proposed. The equalizer is configurable into either a symbol-spaced or fractionally spaced structure. The CMOS chips are full cascadable to implement longer filter lengths without any speed degradation, and the coefficient updating circuitry for implementing the LMS algorithm is included on-chip.Keywords
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