A high-speed CMOS full-adder cell using a new circuit design technique-adaptively-biased pseudo-NMOS logic
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 562-565 vol.1
- https://doi.org/10.1109/iscas.1990.112118
Abstract
A circuit design technique called adaptively biased pseudo-NMOS logic (APNL) is investigated and used in a differential-type full-adder cell design. Based on the layout and simulation results, the APNL full-adder cell is nearly 80% faster than conventional cascode voltage switch logic (CVSL) and over 30% faster than the domino CVSL circuits, while consuming comparable power and silicon area. An application example of the APNL technique is described.Keywords
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