A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (4) , 922-927
- https://doi.org/10.1109/4.34072
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Area-time efficient arithmetic elements for VLSI systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A symmetric submicron CMOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- Prospects of SST technology for high speed LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964