A novel stacked capacitor cell with dual cell plate for 64 Mb DRAMs
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 651-654
- https://doi.org/10.1109/iedm.1990.237115
Abstract
The authors propose a novel stacked capacitor cell with dual cell plate (DCP cell) for 64-Mb DRAMs. The major advantage of this cell is that the dual cell plates completely surround the whole surface of the storage polysilicon, and the storage capacitance of this cell increases significantly compared to the conventional stacked capacitor cell. For a 1.3- mu m/sup 2/ cell, the DCP cell should achieve a storage capacitance of more than 25 fF. The experimental results indicate that the DCP cell can realize the 64-Mb DRAMs and 1.3- mu m/sup 2/ cell area using the 0.3- mu m design rule.<>Keywords
This publication has 2 references indexed in Scilit:
- A 1.28 μm2 bit-line shielded memory cell technology for 64 Mb DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A corrugated capacitor cell (CCC) for megabit dynamic MOS memoriesIEEE Electron Device Letters, 1983