Optimal wiresizing for interconnects with multiple sources
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Performance driven routing with multiple sourcesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimal wiresizing under Elmore delay modelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- Simultaneous gate and interconnect sizing for circuit-level delay optimizationPublished by Association for Computing Machinery (ACM) ,1995
- Simultaneous driver and wire sizing for performance and power optimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
- RC interconnect optimization under the Elmore delay modelPublished by Association for Computing Machinery (ACM) ,1994
- High-performance routing trees with identified critical sinksPublished by Association for Computing Machinery (ACM) ,1993
- Performance-driven interconnect design based on distributed RC delay modelPublished by Association for Computing Machinery (ACM) ,1993
- A new class of iterative Steiner tree heuristics with good performanceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Provably good performance-driven global routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- The Transient Response of Damped Linear Networks with Particular Regard to Wideband AmplifiersJournal of Applied Physics, 1948