0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 675-678
- https://doi.org/10.1109/iedm.1991.235332
Abstract
A 0.1- mu m-gate CMOS/SIMOX (separation by implanted oxygen) has been successfully fabricated using high quality SIMOX substrates and an advanced design concept for the subquarter-micron region based on a simple device model. In addition, both 85-nm-gate n- and p-MOSFETs/SIMOX with 8-nm-thick silicon active layer have been realized. High parasitic resistance in the source and drain regions of the 0.1- mu m-gate CMOS/SIMOX tends to increase the propagation delay time. However, 0.1- mu m-gate CMOS/SIMOX devices with a delay time as low as 10 ps can be obtained by reducing the parasitic resistance.<>Keywords
This publication has 5 references indexed in Scilit:
- Practical reduction of dislocation density in SIMOX wafersElectronics Letters, 1990
- Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gateSolid-State Electronics, 1984
- Theoretical analysis on threshold characteristics of surface-channel MOSFET's fabricated on a buried OxideIEEE Transactions on Electron Devices, 1983
- A two-dimensional analysis for MOSFET's fabricated on buried SiO2layerIEEE Transactions on Electron Devices, 1980
- C.M.O.S. devices fabricated on buried SiO 2 layers formed by oxygen implantation into siliconElectronics Letters, 1978