An Accurate Delay Modeling Technique for Switch-Level Timing Verification

This publication has 6 references indexed in Scilit:

• Crystal: A Timing Analyzer for nMOS VLSI Circuits
  Published by Springer Nature ,1983
• Timing Analysis for nMOS VLSI
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1983
• A Timing Verification System Based on Extracted MOS/VLSI Circuit Parameters
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981
• Verification of timing constraints on large digital systems
  Published by Association for Computing Machinery (ACM) ,1980
• Modeling and simulation of insulated-gate field-effect transistor switching circuits
  IEEE Journal of Solid-State Circuits, 1968
• Pert as an Aid to Logic Design
  IBM Journal of Research and Development, 1966